8 Bit Industry Standard Architecture(ISA) or PC Bus

ISA (Industry Standard Architecture) was first used with the IBM PC in 1981. It was the first open system for PC architecture. No restriction was put on the use of this interconnection method by the IBM. IBM offered free licensing of this PC architecture technique which resulted in more popularity of this. Some main features of 8 bit ISA are:

1) It was introduced by IBM and was the first open system for PC architecture.
2) It provides data transfer rate up to 4.77 Mbps.
3) ISA interface contains 62 pins to interface add on cards. These 62 pins are arranged in two rows, each containing 31 pins.
4) Distance between each pin is 0.1 Inches.
5) 8 Bit ISA make use of Following signals:
    3 Ground Signals
    2 +5V DC Supply
   +12,12,-5V DC supply
    Bidirectional 8 bit data Bus.

   20 Address line, hence memory address space of 1MB (2²⁰=1MB)
   3 DMA request lines
   3 DMA acknowledge lines.
   Six Interrupt Support

Table given below illustrates all signals used by this connector along with their functions:

PIN No.	Signal	Signal Description
B1	Ground	Contains Electrical Ground
B2	RESET DRV	Active Low signal at this pin Resets the Expansion card
B3	+5V DC	+5 V DC Supply
B4	IRQ2	Interrupt Request Line 2
B5	-5 V DC	-5 V DC Supply
B6	DRQ2	DMA request line 2
B7	-12 V DC	-12V DC Supply
B8	CARD SLCTD	It is Zero wait State Signal and is used to synchronize data transfer between Processor and I/O devices.
B9	+12V DC	+12V DC supply
B10	Ground	Electrical Ground Signal
B11	SMEMW	Real Memory Write Signal and is used by the microprocessor to inform expansion board data is placed over data bus and memory controller stores the data byte in addressed location. This signal is active low if memory address is within the lowest 1M of memory address space.
B12	SMEMR	This signal is used by Microprocessor or DMA controller to inform expansion board that memory controller has put the 8 bit data from addressed memory to data bus. This signal is active low if memory address is within the lowest 1M of memory address space.
B13	IOW	I/O read signal informs expansion board that an output device is to receive data byte over the data bus sent by processor.
B14	IOR	I/ O read signal is used to inform expansion board that an input device is moving data through input port, so that processor can read it into its registers.
B15	DACK3	DMA Acknowledge Line 3
B16	DRQ3	DMA Request line 3
B17	DACK1	DMA Acknowledge Line 1
B18	DRQ1	DMA Request Line 1
B19	Refresh	This signal is in active low state if it is bus mastering. It is used to indicate that memory refresh is in progress.
B20	CLK( 4.77MHz)	4.77 MHz clock is provided through crystal oscillator available on motherboard.
B21	IRQ7	Interrupt Request Line 7
B22	IRQ6	Interrupt Request Line 6
B23	IRQ5	Interrupt Request Line 5
B24	IRQ4	Interrupt Request Line 4
B25	IRQ3	Interrupt Request Line 3
B26	DACK2	DMA acknowledge Line 2
B27	T/C	Terminal Count to indicate end of DMA operation
B28	BALE	Bus Address Latch Enable, this signal is used by the processor to read from or write into memory of expansion board.
B29	+5V DC	+5V DC Supply
B30	OSC (14.3 MHz)	This signal of 14.3 MHz is used by the expansion card and is directly connected to the crystal oscillator that is driving the whole motherboard clocks and timers.
B31	Ground	Electrical Ground Signal

These pins are of one row and second row pins are as follows:

Pin No.	Signal	Signal Description
A1	I/O CH CHK	I/O Channel check signal provides Microprocessor the feature of checking status of connected I/O devices with PC bus. Active Low signal generates a non maskable interrupt for Processor
A2	Data Bit 7	Data bit Line 7
A3	Data Bit 6	Data bit Line 6
A4	Data Bit 5	Data bit Line 5
A5	Data Bit 4	Data bit Line 4
A6	Data Bit 3	Data bit Line 3
A7	Data Bit 2	Data bit Line 2
A8	Data Bit 1	Data bit Line 1
A9	Data Bit 0	Data bit Line 0
A10	I/O CH RDY	I/O channel ready signal prevents default ready timer from timing out. This signal is used by memory or I/O to pull read/write cycles.
A11	AEN	Address Enable line is used by the processor to indicate DMA controller that processor has disconnected itself from address bus, data bus and memory and DMA controller can work as bus master.
A12	Address 19	Address Line 19
A13	Address 18	Address Line 18
A14	Address 17	Address Line 17
A15	Address 16	Address Line 16
A16	Address 15	Address Line 15
A17	Address 14	Address Line 14
A18	Address 13	Address Line 13
A19	Address 12	Address Line 12
A20	Address 11	Address Line 11
A21	Address 10	Address Line 10
A22	Address 9	Address Line 9
A23	Address 8	Address Line 8
A24	Address 7	Address Line 7
A25	Address 6	Address Line 6
A26	Address 5	Address Line 5
A27	Address 4	Address Line 4
A28	Address 3	Address Line 3
A29	Address 2	Address Line 2
A30	Address 1	Address Line 1
A31	Address 0	Address Line 0

Expansion Board :

Fig . given below illustrates an 8 bit ISA add on card that can be inserted into ISA slot.

Limitations of 8 Bit ISA

Lower Data Transfer Rate:  8 Bit ISA works at 4.77 MHz and data transfer rate obtained is 4.77Mbps which is very low as compared to today’s standard. Another reason for this slow speed is low bandwidth data Bus (i.e. only 8 bit).

Limited DMA Channels: It support only 3 DMA channels and if one is occupied by CD-Drive and one by HDD than only one DMA channel lefts for Expansion cards.

Less IRQ Support: Only provide six interrupt lines that are very few. If system contains floppy drive, COM port, LPT Port, HDD, CD WR than only one interrupt lefts for the use of expansion boards.

Complex Design: though the installation of ISA expansion card was very easy but the problem associated with them was when more than 1 expansion boards used simultaneously than jumper settings and DIP switches has to be adjusted accordingly.